1. Field of the Invention
The present invention pertains to methods and systems (e.g., programmed computer systems) for device level simulation of semiconductor memory circuits and other circuits comprising MOS transistors.
2. Description of the Related Art
The term “netlist” will be used herein to denote a description of the connectivity of a circuit comprising elements. A netlist consists of predefined elements (e.g., resistors, capacitors, and switches) connected together by “nets.” Each net is a conductor, and will sometimes be referred to herein as a node. The term “graph” will sometimes be used herein to denote a netlist.
Simulation and verification of large semiconductor memory netlists (and other large netlists) whose elements model MOS transistors, voltage sources, resistors, and capacitors has long been a very challenging task. Conventional simulators (e.g., conventional SPICE based simulators) cannot be used effectively to simulate or verify large semiconductor memory circuits since the circuits are usually too large for such simulators to handle. Even conventional simulators which can handle large netlists typically require too much time to simulate and verify a design for a large semiconductor memory circuit, by reading and writing every memory address, and thus are typically impractical to use for this purpose. Also, typical conventional simulators (e.g., SPICE based simulators) cannot detect unknown (“X”) states or high impedance states at nets in electrical circuits of any type. Furthermore, the high degree of accuracy offered by commonly used conventional simulators is typically unnecessary for verification of large semiconductor memory circuits since only functional verification, and not accurate timing and power calculation, is typically required for large semiconductor memory circuit verification.
Typically also, event driven digital simulators (e.g., those based on Verilog) which deal with binary (0 or 1) or ternary (0 or 1 or X, where “X” denotes unknown or undeterminable) values cannot practically be used for simulation and verification of large semiconductor memory netlists (whose elements model MOS transistors, voltage sources, resistors, and capacitors) because the memories modeled by such netlists have custom designs (not standard-cell based designs) so that RTL or gate level Verilog descriptions of the memories do not exist. Even if a switch level Verilog netlist were used, the time required to simulate large semiconductor memory netlists with conventional Verilog simulators is too long, and often results in a crash. Also, switch level Verilog simulation requires accurate strength estimation for correct simulation, which is a difficult task that must be performed manually.
Thus, a fast digital simulator operating on transistor level netlists is the best choice for simulation and verification of large semiconductor memory netlists (and other large netlists) whose elements model MOS transistors, voltage sources, resistors, and capacitors. One such simulator is the conventional IRSIM program. The IRSIM program can detect unknown (X) states and high impedance states at nets, and typically works well to simulate and verify netlists for circuits having standard cell based designs. However, the IRSIM program typically fails when a user attempts to employ it to simulate and verify large semiconductor memory netlists, primarily due to inherent inaccuracies in its delay calculation algorithm.
The expression “MOS transistor circuit” is used herein to denote a circuit including MOS transistors (PMOS and/or NMOS transistors). Gates of at least some of the MOS transistors can be at unknown potentials.
The expression “CCR” (channel connected region) is used herein to denote a circuit that models a MOS transistor circuit and includes no element that is neither a resistor nor a capacitor nor a switch, and whose nodes correspond to nodes of the MOS transistor circuit that are reachable only through transistor source-drain (channel) connections. A CCR is often employed to model a MOS transistor circuit due to the nearly zero gate current of a MOS transistor. The expression “CCR graph” is used herein to denote a netlist that models or represents a CCR, includes no element that is neither a resistor nor a capacitor nor a switch, whose nets (nodes) can have fixed or variable potential, and whose nodes include a fixed node (a “bottom rail”) at a reference potential and another fixed node (a “top rail”) at a fixed potential greater than the reference potential. In FIG. 1, the circuit on the left includes PMOS transistor P1 and NMOS transistor N1. The source of transistor P1 is held at potential Vdd, the drain of transistor P1 is coupled to the drain of NMOS transistor N1, the source of transistor N1 is grounded, and the gates of transistors N1 and P1 are coupled together. A CCR graph on the right side of FIG. 1 models the circuit on the left side of FIG. 1. This CCR graph comprises resistors R1 and R2, switches S1 and S2, and capacitor C0, connected as shown between a top rail (at a potential Vdd above ground potential) and a bottom rail (at ground potential).
The values of each resistor of a CCR graph that represents a channel depends on the type of the channel (N or P), the channel dimensions (length and width), and the logic value at the gate of the transistor modeled by the resistor.
The conventional IRSIM program uses the well-known Elmore delay model to calculate the potential at each node of a CCR, and also the delay associated with a change in potential (at a node of a CCR) in response to a change in potential at another node. The Elmore model uses a simple depth-first-search on the CCR graph to find the effective resistance from a node to the high and low power supplies respectively, and then uses a voltage divider equation to estimate the voltage value at the node. The delay is obtained by multiplying the effective resistance with the effective capacitance. These conventional steps are described below in greater detail. In general, determining the effective resistances using a simple depth-first-search works if and only if the CCR graph contains no loops (i.e., if there is no resistor loop in the RC circuit). If a resistor loop exists, IRSIM heuristically breaks the loop (thus converting the CCR graph into a graph having a tree structure) before applying the Elmore delay model. CCR graphs indicative of memory circuits typically contain resistor loops, and the inaccuracy introduced by heuristically breaking each such loop is unacceptable and causes application of IRSIM to memory circuits to fail.